The present invention relates to a semiconductor memory device in which a pair of inverters is flip-flop-connected thereby to configure an SRAM cell.
In manufacturing the semiconductor device, as a result of advancement of a more refined structure of a transistor owing to evolutions in technologies, there increases variation in characteristic between the transistors adjacent to each other within a semiconductor chip. By the way, stability of the memory cell is attributed to an operating lower limit voltage of the SRAM. Accordingly, it is required for enabling the operation of the SRAM under a much lower operating voltage the stability be improved by restraining variation in characteristic of the memory cell. Then, basically a cell is required to be upsized by increasing a transistor size in the memory cell in order to ensure the stability of the memory cell.
[Patent document 1] Japanese Patent Application Laid-Open Publication No. 2001-257275
[Patent document 2] Japanese Patent Application Laid-Open Publication No. 2003-86713
[Patent document 3] Japanese Patent Application Publication No. 2782682